1. Technical Field
Disclosure generally relates to a semiconductor device and manufacturing method thereof.
2. Description of the Related Art
In order to improve the function of an integrated circuit (IC), it is necessary to improve the performance of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is a component of the IC. The performance of the MISFET has so far been improved by scaling down the size of the MISFET.
The junction characteristic of the semiconductor and the metal in a source electrode and a drain electrode is also improved with the scaling down of the MISFET. Metal-semiconductor compounds such as Nickel monosilicide (herein after Nickel silicide or NiSi) are used as a material for a source/drain electrode. Since the resistivity of NiSi is low and the quantity of Si consumed in a silicidation is small, the metal-semiconductor compound is effective as an ultra-thin electrode material. Pt—NiSi (herein after Nickel platinum silicide and NiPtSi), which includes about 5% to 10% of Pt (platinum) mixed with nickel, is also being currently used. NiPtSi is effective in order to improve the thermal stability, the morphology and the process compatibility.
The resistance of the channel decreases as the channel length of the MISFET becomes shorter. Therefore, the resistance in portions other than a channel, i.e., the resistance of source/drain electrodes which is called parasitic resistance, influences the device performance greatly. In a small-sized MISFET, the contact resistance at an electrode metal/Si junction comprises about the half of the parasitic resistance. Therefore, it is effective to reduce the contact resistance in order to reduce the parasitic resistance. The contact resistance is originated in a Schottky barrier formed at the interface of the electrode metal and a semiconductor.
Then, in order to reduce the contact resistance, it is known to use a material with a low Schottky barrier height (SBH) for the carrier bearing current, as a metallic material of an electrode. The SBH of the NiSi/Si interface for electrons is a relatively high value, 0.65 eV. If NiPtSi is used, the Schottky barrier for electrons will become still higher. On the other hand, if a rare earth metal silicide, such as erbium silicide, is used as a metallic material of an electrode, the Schottky barrier for electrons will be reduced to about 0.3 eV.
However, the rare earth metal silicide cannot achieve desirable characteristics from viewpoints of leakage current, resistance, etc. Furthermore, it is necessary to use two metal silicides. That is, one with a low Schottky barrier for electrons is used for a n-type device, and another metal silicide with a low Schottky barrier for holes is used for a p-type device. For this reason, the cost is too high and the technical use of the two metal silicides is difficult.
Introducing impurities into the interface between Si and the electrode of NiSi or NiPtSi has been proposed for reducing the contact resistance. For a p-type MISFET, in order to reduce the Schottky barrier of a hole, introducing group II elements, such as Mg and Ca, is proposed. For an n-type MISFET, in order to reduce an electron Schottky barrier, introducing group VI elements, such as S (sulfur) and Se (selenium), is proposed. Especially by introducing S, it is considered that surface states are formed near the conduction band of Si and the Fermi level is pinned, and the biggest effect may be obtained to reduce the Schottky barrier for electrons.
The following method can be considered to introduce S into a silicide/Si interface. S ions are injected into the portion which forms the electrode on a Si substrate, activation annealing is performed if needed, a thin film of metal, such as nickel, is formed, and after that, the metal is made to react with the substrate silicon (silicidation) by heat treatment to form the silicide electrode. At this time, S segregates to a silicide/Si interface according to what is called a snow-plow effect. Although the method of the above-mentioned snow-plow effect is used also for other impurities, there are several problems, as described below.
First, the diffusion of S in Si is very fast. In an n-type MISFET, donor impurities, such as As and P, are introduced into the portion which forms the electrode on a Si substrate, and activation annealing is performed. However, S is immediately spread in this activation annealing, most of the S escapes away from a substrate face, and a dose loss takes place.
Then, another method of implanting S after activating As and P is also considered. However, when a silicide/Si interface moves toward the substrate during silicidation, S atoms are pushed downward into the substrate due to the snow-plow effect. Since S, an easily diffused impurity, spreads and is distributed into the substrate by this effect, its segregation peak becomes broad. For this reason, S concentration of an interface does not only become high, but it becomes a cause of leakage, since S is distributed deeply.
In order to avoid S density lowering in the interface by a dose loss, another method of enlarging the S injection rate is also considered. However, if an injection rate is enlarged, the defect in a Si substrate will increase, and it will become a cause of leakage.
Furthermore, there is another problem that S diffuses deeply in the substrate since S ions are implanted directly into Si. Especially because S is an element with the almost same mass as Si, it is easy to diffuse S deeply in the substrate. If S diffuses deeply, it will cause junction leakage and so on, and the tolerance of the short channel effect will deteriorate.
In order to avoid the above-mentioned problem, using Se is suggested (reference 1; H.-S. Wong, et al., IEEE Elec. Dev. Lett. 28 vo. 12, pp. 1102-1104 (2007)). Since Se has about 2.4 times the mass of S, the profile at the time of injection does not spread easily, and its diffusion is also small. However, even if Se is used, the Schottky barrier height for electrons is about 0.1 eV. In the technology node below the 22-nm generation where the contact resistance degrades the device performance, using Se is expected to reduce the barrier height further.
On the other hand, the method of injecting S into Si through NiSi and avoiding the above-mentioned problem is also considered in JP-A No. 2008-131051.
In JP-A No. 2008-131051, S ions are implanted after forming NiSi, without performing heat treatment which can rearrange S. In this case, almost all S ions are implanted into interstitial sites and do not form interface states. Moreover, there is another problem that electric resistance may go up as a whole, since Si and NiSi of an electrode field may be damaged.